forked from forgejo/forgejo
Add a storage layer for attachments (#11387)
* Add a storage layer for attachments * Fix some bug * fix test * Fix copyright head and lint * Fix bug * Add setting for minio and flags for migrate-storage * Add documents * fix lint * Add test for minio store type on attachments * fix test * fix test * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Add warning when storage migrated successfully * Fix drone * fix test * rebase * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * refactor the codes * add trace * Fix test * remove log on xorm * Fi download bug * Add a storage layer for attachments * Add setting for minio and flags for migrate-storage * fix lint * Add test for minio store type on attachments * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Fix drone * fix test * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * refactor the codes * add trace * Fix test * Add URL function to serve attachments directly from S3/Minio * Add ability to enable/disable redirection in attachment configuration * Fix typo * Add a storage layer for attachments * Add setting for minio and flags for migrate-storage * fix lint * Add test for minio store type on attachments * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Fix drone * fix test * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * don't change unrelated files * Fix lint * Fix build * update go.mod and go.sum * Use github.com/minio/minio-go/v6 * Remove unused function * Upgrade minio to v7 and some other improvements * fix lint * Fix go mod Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> Co-authored-by: Tyler <tystuyfzand@gmail.com>
This commit is contained in:
Lunny Xiao
GitHub
parent
02fbe1e5dc
commit
62e6c9bc6c
330 changed files with 62099 additions and 331 deletions
408
vendor/github.com/minio/sha256-simd/sha256blockAvx_amd64.s
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vendored
Normal file
408
vendor/github.com/minio/sha256-simd/sha256blockAvx_amd64.s
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//+build !noasm,!appengine
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// SHA256 implementation for AVX
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//
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// Minio Cloud Storage, (C) 2016 Minio, Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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//
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// This code is based on an Intel White-Paper:
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// "Fast SHA-256 Implementations on Intel Architecture Processors"
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//
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// together with the reference implementation from the following authors:
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// James Guilford <james.guilford@intel.com>
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// Kirk Yap <kirk.s.yap@intel.com>
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// Tim Chen <tim.c.chen@linux.intel.com>
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//
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// For Golang it has been converted to Plan 9 assembly with the help of
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// github.com/minio/asm2plan9s to assemble Intel instructions to their Plan9
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// equivalents
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//
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#include "textflag.h"
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#define ROTATE_XS \
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MOVOU X4, X15 \
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MOVOU X5, X4 \
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MOVOU X6, X5 \
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MOVOU X7, X6 \
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MOVOU X15, X7
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// compute s0 four at a time and s1 two at a time
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// compute W[-16] + W[-7] 4 at a time
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#define FOUR_ROUNDS_AND_SCHED(a, b, c, d, e, f, g, h) \
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MOVL e, R13 \ // y0 = e
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ROLL $18, R13 \ // y0 = e >> (25-11)
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MOVL a, R14 \ // y1 = a
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LONG $0x0f41e3c4; WORD $0x04c6 \ // VPALIGNR XMM0,XMM7,XMM6,0x4 /* XTMP0 = W[-7] */
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ROLL $23, R14 \ // y1 = a >> (22-13)
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XORL e, R13 \ // y0 = e ^ (e >> (25-11))
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MOVL f, R15 \ // y2 = f
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ROLL $27, R13 \ // y0 = (e >> (11-6)) ^ (e >> (25-6))
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XORL a, R14 \ // y1 = a ^ (a >> (22-13)
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XORL g, R15 \ // y2 = f^g
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LONG $0xc4fef9c5 \ // VPADDD XMM0,XMM0,XMM4 /* XTMP0 = W[-7] + W[-16] */
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XORL e, R13 \ // y0 = e ^ (e >> (11-6)) ^ (e >> (25-6) )
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ANDL e, R15 \ // y2 = (f^g)&e
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ROLL $21, R14 \ // y1 = (a >> (13-2)) ^ (a >> (22-2))
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\
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\ // compute s0
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\
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LONG $0x0f51e3c4; WORD $0x04cc \ // VPALIGNR XMM1,XMM5,XMM4,0x4 /* XTMP1 = W[-15] */
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XORL a, R14 \ // y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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ROLL $26, R13 \ // y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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XORL g, R15 \ // y2 = CH = ((f^g)&e)^g
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ROLL $30, R14 \ // y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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ADDL R13, R15 \ // y2 = S1 + CH
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ADDL _xfer+48(FP), R15 \ // y2 = k + w + S1 + CH
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MOVL a, R13 \ // y0 = a
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ADDL R15, h \ // h = h + S1 + CH + k + w
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\ // ROTATE_ARGS
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MOVL a, R15 \ // y2 = a
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LONG $0xd172e9c5; BYTE $0x07 \ // VPSRLD XMM2,XMM1,0x7 /* */
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ORL c, R13 \ // y0 = a|c
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ADDL h, d \ // d = d + h + S1 + CH + k + w
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ANDL c, R15 \ // y2 = a&c
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LONG $0xf172e1c5; BYTE $0x19 \ // VPSLLD XMM3,XMM1,0x19 /* */
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ANDL b, R13 \ // y0 = (a|c)&b
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ADDL R14, h \ // h = h + S1 + CH + k + w + S0
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LONG $0xdaebe1c5 \ // VPOR XMM3,XMM3,XMM2 /* XTMP1 = W[-15] MY_ROR 7 */
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ORL R15, R13 \ // y0 = MAJ = (a|c)&b)|(a&c)
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ADDL R13, h \ // h = h + S1 + CH + k + w + S0 + MAJ
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\ // ROTATE_ARGS
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MOVL d, R13 \ // y0 = e
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MOVL h, R14 \ // y1 = a
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ROLL $18, R13 \ // y0 = e >> (25-11)
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XORL d, R13 \ // y0 = e ^ (e >> (25-11))
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MOVL e, R15 \ // y2 = f
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ROLL $23, R14 \ // y1 = a >> (22-13)
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LONG $0xd172e9c5; BYTE $0x12 \ // VPSRLD XMM2,XMM1,0x12 /* */
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XORL h, R14 \ // y1 = a ^ (a >> (22-13)
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ROLL $27, R13 \ // y0 = (e >> (11-6)) ^ (e >> (25-6))
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XORL f, R15 \ // y2 = f^g
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LONG $0xd172b9c5; BYTE $0x03 \ // VPSRLD XMM8,XMM1,0x3 /* XTMP4 = W[-15] >> 3 */
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ROLL $21, R14 \ // y1 = (a >> (13-2)) ^ (a >> (22-2))
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XORL d, R13 \ // y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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ANDL d, R15 \ // y2 = (f^g)&e
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ROLL $26, R13 \ // y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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LONG $0xf172f1c5; BYTE $0x0e \ // VPSLLD XMM1,XMM1,0xe /* */
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XORL h, R14 \ // y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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XORL f, R15 \ // y2 = CH = ((f^g)&e)^g
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LONG $0xd9efe1c5 \ // VPXOR XMM3,XMM3,XMM1 /* */
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ADDL R13, R15 \ // y2 = S1 + CH
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ADDL _xfer+52(FP), R15 \ // y2 = k + w + S1 + CH
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ROLL $30, R14 \ // y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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LONG $0xdaefe1c5 \ // VPXOR XMM3,XMM3,XMM2 /* XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR */
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MOVL h, R13 \ // y0 = a
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ADDL R15, g \ // h = h + S1 + CH + k + w
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MOVL h, R15 \ // y2 = a
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LONG $0xef61c1c4; BYTE $0xc8 \ // VPXOR XMM1,XMM3,XMM8 /* XTMP1 = s0 */
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ORL b, R13 \ // y0 = a|c
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ADDL g, c \ // d = d + h + S1 + CH + k + w
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ANDL b, R15 \ // y2 = a&c
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\
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\ // compute low s1
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\
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LONG $0xd770f9c5; BYTE $0xfa \ // VPSHUFD XMM2,XMM7,0xfa /* XTMP2 = W[-2] {BBAA} */
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ANDL a, R13 \ // y0 = (a|c)&b
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ADDL R14, g \ // h = h + S1 + CH + k + w + S0
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LONG $0xc1fef9c5 \ // VPADDD XMM0,XMM0,XMM1 /* XTMP0 = W[-16] + W[-7] + s0 */
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ORL R15, R13 \ // y0 = MAJ = (a|c)&b)|(a&c)
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ADDL R13, g \ // h = h + S1 + CH + k + w + S0 + MAJ
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\ // ROTATE_ARGS
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MOVL c, R13 \ // y0 = e
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MOVL g, R14 \ // y1 = a
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ROLL $18, R13 \ // y0 = e >> (25-11)
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XORL c, R13 \ // y0 = e ^ (e >> (25-11))
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ROLL $23, R14 \ // y1 = a >> (22-13)
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MOVL d, R15 \ // y2 = f
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XORL g, R14 \ // y1 = a ^ (a >> (22-13)
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ROLL $27, R13 \ // y0 = (e >> (11-6)) ^ (e >> (25-6))
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LONG $0xd272b9c5; BYTE $0x0a \ // VPSRLD XMM8,XMM2,0xa /* XTMP4 = W[-2] >> 10 {BBAA} */
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XORL e, R15 \ // y2 = f^g
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LONG $0xd273e1c5; BYTE $0x13 \ // VPSRLQ XMM3,XMM2,0x13 /* XTMP3 = W[-2] MY_ROR 19 {xBxA} */
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XORL c, R13 \ // y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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ANDL c, R15 \ // y2 = (f^g)&e
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LONG $0xd273e9c5; BYTE $0x11 \ // VPSRLQ XMM2,XMM2,0x11 /* XTMP2 = W[-2] MY_ROR 17 {xBxA} */
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ROLL $21, R14 \ // y1 = (a >> (13-2)) ^ (a >> (22-2))
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XORL g, R14 \ // y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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XORL e, R15 \ // y2 = CH = ((f^g)&e)^g
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ROLL $26, R13 \ // y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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LONG $0xd3efe9c5 \ // VPXOR XMM2,XMM2,XMM3 /* */
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ADDL R13, R15 \ // y2 = S1 + CH
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ROLL $30, R14 \ // y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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ADDL _xfer+56(FP), R15 \ // y2 = k + w + S1 + CH
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LONG $0xc2ef39c5 \ // VPXOR XMM8,XMM8,XMM2 /* XTMP4 = s1 {xBxA} */
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MOVL g, R13 \ // y0 = a
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ADDL R15, f \ // h = h + S1 + CH + k + w
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MOVL g, R15 \ // y2 = a
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LONG $0x003942c4; BYTE $0xc2 \ // VPSHUFB XMM8,XMM8,XMM10 /* XTMP4 = s1 {00BA} */
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ORL a, R13 \ // y0 = a|c
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ADDL f, b \ // d = d + h + S1 + CH + k + w
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ANDL a, R15 \ // y2 = a&c
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LONG $0xfe79c1c4; BYTE $0xc0 \ // VPADDD XMM0,XMM0,XMM8 /* XTMP0 = {..., ..., W[1], W[0]} */
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ANDL h, R13 \ // y0 = (a|c)&b
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ADDL R14, f \ // h = h + S1 + CH + k + w + S0
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\
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\ // compute high s1
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\
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LONG $0xd070f9c5; BYTE $0x50 \ // VPSHUFD XMM2,XMM0,0x50 /* XTMP2 = W[-2] {DDCC} */
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ORL R15, R13 \ // y0 = MAJ = (a|c)&b)|(a&c)
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ADDL R13, f \ // h = h + S1 + CH + k + w + S0 + MAJ
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\ // ROTATE_ARGS
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MOVL b, R13 \ // y0 = e
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ROLL $18, R13 \ // y0 = e >> (25-11)
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MOVL f, R14 \ // y1 = a
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ROLL $23, R14 \ // y1 = a >> (22-13)
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XORL b, R13 \ // y0 = e ^ (e >> (25-11))
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MOVL c, R15 \ // y2 = f
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ROLL $27, R13 \ // y0 = (e >> (11-6)) ^ (e >> (25-6))
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LONG $0xd272a1c5; BYTE $0x0a \ // VPSRLD XMM11,XMM2,0xa /* XTMP5 = W[-2] >> 10 {DDCC} */
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XORL f, R14 \ // y1 = a ^ (a >> (22-13)
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XORL d, R15 \ // y2 = f^g
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LONG $0xd273e1c5; BYTE $0x13 \ // VPSRLQ XMM3,XMM2,0x13 /* XTMP3 = W[-2] MY_ROR 19 {xDxC} */
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XORL b, R13 \ // y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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ANDL b, R15 \ // y2 = (f^g)&e
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ROLL $21, R14 \ // y1 = (a >> (13-2)) ^ (a >> (22-2))
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LONG $0xd273e9c5; BYTE $0x11 \ // VPSRLQ XMM2,XMM2,0x11 /* XTMP2 = W[-2] MY_ROR 17 {xDxC} */
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XORL f, R14 \ // y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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ROLL $26, R13 \ // y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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XORL d, R15 \ // y2 = CH = ((f^g)&e)^g
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LONG $0xd3efe9c5 \ // VPXOR XMM2,XMM2,XMM3 /* */
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ROLL $30, R14 \ // y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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ADDL R13, R15 \ // y2 = S1 + CH
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ADDL _xfer+60(FP), R15 \ // y2 = k + w + S1 + CH
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LONG $0xdaef21c5 \ // VPXOR XMM11,XMM11,XMM2 /* XTMP5 = s1 {xDxC} */
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MOVL f, R13 \ // y0 = a
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ADDL R15, e \ // h = h + S1 + CH + k + w
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MOVL f, R15 \ // y2 = a
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LONG $0x002142c4; BYTE $0xdc \ // VPSHUFB XMM11,XMM11,XMM12 /* XTMP5 = s1 {DC00} */
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ORL h, R13 \ // y0 = a|c
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ADDL e, a \ // d = d + h + S1 + CH + k + w
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ANDL h, R15 \ // y2 = a&c
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LONG $0xe0fea1c5 \ // VPADDD XMM4,XMM11,XMM0 /* X0 = {W[3], W[2], W[1], W[0]} */
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ANDL g, R13 \ // y0 = (a|c)&b
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ADDL R14, e \ // h = h + S1 + CH + k + w + S0
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ORL R15, R13 \ // y0 = MAJ = (a|c)&b)|(a&c)
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ADDL R13, e \ // h = h + S1 + CH + k + w + S0 + MAJ
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\ // ROTATE_ARGS
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ROTATE_XS
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#define DO_ROUND(a, b, c, d, e, f, g, h, offset) \
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MOVL e, R13 \ // y0 = e
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ROLL $18, R13 \ // y0 = e >> (25-11)
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MOVL a, R14 \ // y1 = a
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XORL e, R13 \ // y0 = e ^ (e >> (25-11))
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ROLL $23, R14 \ // y1 = a >> (22-13)
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MOVL f, R15 \ // y2 = f
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XORL a, R14 \ // y1 = a ^ (a >> (22-13)
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ROLL $27, R13 \ // y0 = (e >> (11-6)) ^ (e >> (25-6))
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XORL g, R15 \ // y2 = f^g
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XORL e, R13 \ // y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
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ROLL $21, R14 \ // y1 = (a >> (13-2)) ^ (a >> (22-2))
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ANDL e, R15 \ // y2 = (f^g)&e
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XORL a, R14 \ // y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
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ROLL $26, R13 \ // y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
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XORL g, R15 \ // y2 = CH = ((f^g)&e)^g
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ADDL R13, R15 \ // y2 = S1 + CH
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ROLL $30, R14 \ // y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
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ADDL _xfer+offset(FP), R15 \ // y2 = k + w + S1 + CH
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MOVL a, R13 \ // y0 = a
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ADDL R15, h \ // h = h + S1 + CH + k + w
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MOVL a, R15 \ // y2 = a
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ORL c, R13 \ // y0 = a|c
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ADDL h, d \ // d = d + h + S1 + CH + k + w
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ANDL c, R15 \ // y2 = a&c
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ANDL b, R13 \ // y0 = (a|c)&b
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ADDL R14, h \ // h = h + S1 + CH + k + w + S0
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ORL R15, R13 \ // y0 = MAJ = (a|c)&b)|(a&c)
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ADDL R13, h // h = h + S1 + CH + k + w + S0 + MAJ
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// func blockAvx(h []uint32, message []uint8, reserved0, reserved1, reserved2, reserved3 uint64)
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TEXT ·blockAvx(SB), 7, $0-80
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MOVQ h+0(FP), SI // SI: &h
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MOVQ message_base+24(FP), R8 // &message
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MOVQ message_len+32(FP), R9 // length of message
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CMPQ R9, $0
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JEQ done_hash
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ADDQ R8, R9
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MOVQ R9, reserved2+64(FP) // store end of message
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// Register definition
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// a --> eax
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// b --> ebx
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// c --> ecx
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// d --> r8d
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// e --> edx
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// f --> r9d
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// g --> r10d
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// h --> r11d
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//
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// y0 --> r13d
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// y1 --> r14d
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// y2 --> r15d
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MOVL (0*4)(SI), AX // a = H0
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MOVL (1*4)(SI), BX // b = H1
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MOVL (2*4)(SI), CX // c = H2
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MOVL (3*4)(SI), R8 // d = H3
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MOVL (4*4)(SI), DX // e = H4
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MOVL (5*4)(SI), R9 // f = H5
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MOVL (6*4)(SI), R10 // g = H6
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MOVL (7*4)(SI), R11 // h = H7
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MOVOU bflipMask<>(SB), X13
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MOVOU shuf00BA<>(SB), X10 // shuffle xBxA -> 00BA
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MOVOU shufDC00<>(SB), X12 // shuffle xDxC -> DC00
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MOVQ message_base+24(FP), SI // SI: &message
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||||
|
||||
loop0:
|
||||
LEAQ constants<>(SB), BP
|
||||
|
||||
// byte swap first 16 dwords
|
||||
MOVOU 0*16(SI), X4
|
||||
LONG $0x0059c2c4; BYTE $0xe5 // VPSHUFB XMM4, XMM4, XMM13
|
||||
MOVOU 1*16(SI), X5
|
||||
LONG $0x0051c2c4; BYTE $0xed // VPSHUFB XMM5, XMM5, XMM13
|
||||
MOVOU 2*16(SI), X6
|
||||
LONG $0x0049c2c4; BYTE $0xf5 // VPSHUFB XMM6, XMM6, XMM13
|
||||
MOVOU 3*16(SI), X7
|
||||
LONG $0x0041c2c4; BYTE $0xfd // VPSHUFB XMM7, XMM7, XMM13
|
||||
|
||||
MOVQ SI, reserved3+72(FP)
|
||||
MOVD $0x3, DI
|
||||
|
||||
// schedule 48 input dwords, by doing 3 rounds of 16 each
|
||||
loop1:
|
||||
LONG $0x4dfe59c5; BYTE $0x00 // VPADDD XMM9, XMM4, 0[RBP] /* Add 1st constant to first part of message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
FOUR_ROUNDS_AND_SCHED(AX, BX, CX, R8, DX, R9, R10, R11)
|
||||
|
||||
LONG $0x4dfe59c5; BYTE $0x10 // VPADDD XMM9, XMM4, 16[RBP] /* Add 2nd constant to message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
FOUR_ROUNDS_AND_SCHED(DX, R9, R10, R11, AX, BX, CX, R8)
|
||||
|
||||
LONG $0x4dfe59c5; BYTE $0x20 // VPADDD XMM9, XMM4, 32[RBP] /* Add 3rd constant to message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
FOUR_ROUNDS_AND_SCHED(AX, BX, CX, R8, DX, R9, R10, R11)
|
||||
|
||||
LONG $0x4dfe59c5; BYTE $0x30 // VPADDD XMM9, XMM4, 48[RBP] /* Add 4th constant to message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
ADDQ $64, BP
|
||||
FOUR_ROUNDS_AND_SCHED(DX, R9, R10, R11, AX, BX, CX, R8)
|
||||
|
||||
SUBQ $1, DI
|
||||
JNE loop1
|
||||
|
||||
MOVD $0x2, DI
|
||||
|
||||
loop2:
|
||||
LONG $0x4dfe59c5; BYTE $0x00 // VPADDD XMM9, XMM4, 0[RBP] /* Add 1st constant to first part of message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
DO_ROUND( AX, BX, CX, R8, DX, R9, R10, R11, 48)
|
||||
DO_ROUND(R11, AX, BX, CX, R8, DX, R9, R10, 52)
|
||||
DO_ROUND(R10, R11, AX, BX, CX, R8, DX, R9, 56)
|
||||
DO_ROUND( R9, R10, R11, AX, BX, CX, R8, DX, 60)
|
||||
|
||||
LONG $0x4dfe51c5; BYTE $0x10 // VPADDD XMM9, XMM5, 16[RBP] /* Add 2nd constant to message */
|
||||
MOVOU X9, reserved0+48(FP)
|
||||
ADDQ $32, BP
|
||||
DO_ROUND( DX, R9, R10, R11, AX, BX, CX, R8, 48)
|
||||
DO_ROUND( R8, DX, R9, R10, R11, AX, BX, CX, 52)
|
||||
DO_ROUND( CX, R8, DX, R9, R10, R11, AX, BX, 56)
|
||||
DO_ROUND( BX, CX, R8, DX, R9, R10, R11, AX, 60)
|
||||
|
||||
MOVOU X6, X4
|
||||
MOVOU X7, X5
|
||||
|
||||
SUBQ $1, DI
|
||||
JNE loop2
|
||||
|
||||
MOVQ h+0(FP), SI // SI: &h
|
||||
ADDL (0*4)(SI), AX // H0 = a + H0
|
||||
MOVL AX, (0*4)(SI)
|
||||
ADDL (1*4)(SI), BX // H1 = b + H1
|
||||
MOVL BX, (1*4)(SI)
|
||||
ADDL (2*4)(SI), CX // H2 = c + H2
|
||||
MOVL CX, (2*4)(SI)
|
||||
ADDL (3*4)(SI), R8 // H3 = d + H3
|
||||
MOVL R8, (3*4)(SI)
|
||||
ADDL (4*4)(SI), DX // H4 = e + H4
|
||||
MOVL DX, (4*4)(SI)
|
||||
ADDL (5*4)(SI), R9 // H5 = f + H5
|
||||
MOVL R9, (5*4)(SI)
|
||||
ADDL (6*4)(SI), R10 // H6 = g + H6
|
||||
MOVL R10, (6*4)(SI)
|
||||
ADDL (7*4)(SI), R11 // H7 = h + H7
|
||||
MOVL R11, (7*4)(SI)
|
||||
|
||||
MOVQ reserved3+72(FP), SI
|
||||
ADDQ $64, SI
|
||||
CMPQ reserved2+64(FP), SI
|
||||
JNE loop0
|
||||
|
||||
done_hash:
|
||||
RET
|
||||
|
||||
// Constants table
|
||||
DATA constants<>+0x0(SB)/8, $0x71374491428a2f98
|
||||
DATA constants<>+0x8(SB)/8, $0xe9b5dba5b5c0fbcf
|
||||
DATA constants<>+0x10(SB)/8, $0x59f111f13956c25b
|
||||
DATA constants<>+0x18(SB)/8, $0xab1c5ed5923f82a4
|
||||
DATA constants<>+0x20(SB)/8, $0x12835b01d807aa98
|
||||
DATA constants<>+0x28(SB)/8, $0x550c7dc3243185be
|
||||
DATA constants<>+0x30(SB)/8, $0x80deb1fe72be5d74
|
||||
DATA constants<>+0x38(SB)/8, $0xc19bf1749bdc06a7
|
||||
DATA constants<>+0x40(SB)/8, $0xefbe4786e49b69c1
|
||||
DATA constants<>+0x48(SB)/8, $0x240ca1cc0fc19dc6
|
||||
DATA constants<>+0x50(SB)/8, $0x4a7484aa2de92c6f
|
||||
DATA constants<>+0x58(SB)/8, $0x76f988da5cb0a9dc
|
||||
DATA constants<>+0x60(SB)/8, $0xa831c66d983e5152
|
||||
DATA constants<>+0x68(SB)/8, $0xbf597fc7b00327c8
|
||||
DATA constants<>+0x70(SB)/8, $0xd5a79147c6e00bf3
|
||||
DATA constants<>+0x78(SB)/8, $0x1429296706ca6351
|
||||
DATA constants<>+0x80(SB)/8, $0x2e1b213827b70a85
|
||||
DATA constants<>+0x88(SB)/8, $0x53380d134d2c6dfc
|
||||
DATA constants<>+0x90(SB)/8, $0x766a0abb650a7354
|
||||
DATA constants<>+0x98(SB)/8, $0x92722c8581c2c92e
|
||||
DATA constants<>+0xa0(SB)/8, $0xa81a664ba2bfe8a1
|
||||
DATA constants<>+0xa8(SB)/8, $0xc76c51a3c24b8b70
|
||||
DATA constants<>+0xb0(SB)/8, $0xd6990624d192e819
|
||||
DATA constants<>+0xb8(SB)/8, $0x106aa070f40e3585
|
||||
DATA constants<>+0xc0(SB)/8, $0x1e376c0819a4c116
|
||||
DATA constants<>+0xc8(SB)/8, $0x34b0bcb52748774c
|
||||
DATA constants<>+0xd0(SB)/8, $0x4ed8aa4a391c0cb3
|
||||
DATA constants<>+0xd8(SB)/8, $0x682e6ff35b9cca4f
|
||||
DATA constants<>+0xe0(SB)/8, $0x78a5636f748f82ee
|
||||
DATA constants<>+0xe8(SB)/8, $0x8cc7020884c87814
|
||||
DATA constants<>+0xf0(SB)/8, $0xa4506ceb90befffa
|
||||
DATA constants<>+0xf8(SB)/8, $0xc67178f2bef9a3f7
|
||||
|
||||
DATA bflipMask<>+0x00(SB)/8, $0x0405060700010203
|
||||
DATA bflipMask<>+0x08(SB)/8, $0x0c0d0e0f08090a0b
|
||||
|
||||
DATA shuf00BA<>+0x00(SB)/8, $0x0b0a090803020100
|
||||
DATA shuf00BA<>+0x08(SB)/8, $0xFFFFFFFFFFFFFFFF
|
||||
|
||||
DATA shufDC00<>+0x00(SB)/8, $0xFFFFFFFFFFFFFFFF
|
||||
DATA shufDC00<>+0x08(SB)/8, $0x0b0a090803020100
|
||||
|
||||
GLOBL constants<>(SB), 8, $256
|
||||
GLOBL bflipMask<>(SB), (NOPTR+RODATA), $16
|
||||
GLOBL shuf00BA<>(SB), (NOPTR+RODATA), $16
|
||||
GLOBL shufDC00<>(SB), (NOPTR+RODATA), $16
|
||||
Loading…
Add table
Add a link
Reference in a new issue