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go1.16 (#14783)

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techknowlogick 2021-02-28 18:08:33 -05:00 • committed by GitHub
parent 030646eea4
commit 47f6a4ec3f
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36
vendor/github.com/minio/md5-simd/block8_amd64.s generated vendored
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@ -1,3 +1,5 @@
//+build !noasm,!appengine,gc
// Copyright (c) 2018 Igneous Systems
// MIT License
//
@ -70,7 +72,7 @@ TEXT ·block8(SB), 4, $0-40
#define consts DI
#define prepmask \
VXORPS mask, mask, mask \
VPXOR mask, mask, mask \
VPCMPGTD mask, off, mask
#define prep(index) \
@ -86,14 +88,14 @@ TEXT ·block8(SB), 4, $0-40
#define roll(shift, a) \
VPSLLD $shift, a, rtmp1 \
VPSRLD $32-shift, a, a \
VORPS rtmp1, a, a
VPOR rtmp1, a, a
#define ROUND1(a, b, c, d, index, const, shift) \
VXORPS c, tmp, tmp \
VPXOR c, tmp, tmp \
VPADDD 32*const(consts), a, a \
VPADDD mem, a, a \
VANDPS b, tmp, tmp \
VXORPS d, tmp, tmp \
VPAND b, tmp, tmp \
VPXOR d, tmp, tmp \
prep(index) \
VPADDD tmp, a, a \
roll(shift,a) \
@ -101,11 +103,11 @@ TEXT ·block8(SB), 4, $0-40
VPADDD b, a, a
#define ROUND1load(a, b, c, d, index, const, shift) \
VXORPS c, tmp, tmp \
VXORPD c, tmp, tmp \
VPADDD 32*const(consts), a, a \
VPADDD mem, a, a \
VANDPS b, tmp, tmp \
VXORPS d, tmp, tmp \
VPAND b, tmp, tmp \
VPXOR d, tmp, tmp \
load(index) \
VPADDD tmp, a, a \
roll(shift,a) \
@ -115,10 +117,10 @@ TEXT ·block8(SB), 4, $0-40
#define ROUND2(a, b, c, d, index, const, shift) \
VPADDD 32*const(consts), a, a \
VPADDD mem, a, a \
VANDPS b, tmp2, tmp2 \
VANDNPS c, tmp, tmp \
VPAND b, tmp2, tmp2 \
VANDNPD c, tmp, tmp \
load(index) \
VORPS tmp, tmp2, tmp2 \
VPOR tmp, tmp2, tmp2 \
VMOVAPD c, tmp \
VPADDD tmp2, a, a \
VMOVAPD c, tmp2 \
@ -129,8 +131,8 @@ TEXT ·block8(SB), 4, $0-40
VPADDD 32*const(consts), a, a \
VPADDD mem, a, a \
load(index) \
VXORPS d, tmp, tmp \
VXORPS b, tmp, tmp \
VPXOR d, tmp, tmp \
VPXOR b, tmp, tmp \
VPADDD tmp, a, a \
roll(shift,a) \
VMOVAPD b, tmp \
@ -139,12 +141,12 @@ TEXT ·block8(SB), 4, $0-40
#define ROUND4(a, b, c, d, index, const, shift) \
VPADDD 32*const(consts), a, a \
VPADDD mem, a, a \
VORPS b, tmp, tmp \
VXORPS c, tmp, tmp \
VPOR b, tmp, tmp \
VPXOR c, tmp, tmp \
VPADDD tmp, a, a \
load(index) \
roll(shift,a) \
VXORPS c, ones, tmp \
VPXOR c, ones, tmp \
VPADDD b, a, a
// load digest into state registers
@ -242,7 +244,7 @@ loop:
ROUND3(b,c,d,a, 0,0x2f,23)
load(0)
VXORPS d, ones, tmp
VPXOR d, ones, tmp
ROUND4(a,b,c,d, 7,0x30, 6)
ROUND4(d,a,b,c,14,0x31,10)